TinyRISCV A very simple implementation by Liang Kangnan
This project implements a single-core 32-bit small RISC-V processor core [...]
This project implements a single-core 32-bit small RISC-V processor core [...]
SSRV(Super-Scalar RISC-V) --- Super-scalar out-of-order RV32IMC CPU core, performance: 6.4 [...]
The SHAKTI Processor Program, was started as an academic initiative [...]
This post contains the RiscyOO processor written in Bluespec System [...]
Based on Chisel3, Rift2Core is a 9-stage, N-issue(Configurable), out-of-order, 64-bits [...]
ReonV is a modified version of the Leon3, a synthesizable VHDL [...]