This project implements a single-core 32-bit small RISC-V processor core (tinyriscv), written in verilog language. The design goal is to benchmark ARM Cortex-M3 series processors. tinyriscv has the following features:

 

  1. Support RV32IM instruction set, passed RISC-V instruction compatibility test;
  2. Three-stage pipeline is adopted, that is, instruction fetching, decoding, and execution;
  3. Can run C language programs;
  4. Support JTAG, you can read and write memory through openocd (online update program);
  5. support interrupts;
  6. Support bus;
  7. Support FreeRTOS;
  8. Support program update via serial port;
  9. Easy portability to any FPGA platform (if resources are sufficient);

 

You can check out the TinyRiscV core here