SSRV(Super-Scalar RISC-V) — Super-scalar out-of-order RV32IMC CPU core, performance: 6.4 CoreMark/MHz.

 

Feature
  • Its instruction set is RV32IMC.
  • Synthesizable verilog description.

 

 

SSRV is an instruction set processing architecture for RV32IMC. Its main architecture is four buffers linked together, with an instruction bus configured as 32*N bit and a fixed 32 bit data bus. It has corresponding performance as long as the following parameters are configured:

 

  • INSTR_MISALLIGNED — Whether the instruction bus is in misaligned mode.
  • FETCH_REGISTERED — Whether the first buffer registers its output.
  • MULT_NUM — The number of hardware MUL/DIV modules.
  • The ‘instrbits’ buffer — （input/capacity/output）
  • The ‘schedule’ buffer — （input/capacity/output）
  • The ‘membuf’ buffer — （input/capacity/output）
  • The ‘mprf’ buffer — （input/capacity/output）

 

You can download the SSRV core here