UltraEmbedded presents a 32-bit RISC-V core written in Verilog and an instruction set simulator supporting RV32IM.
This core has been tested against a co-simulation model and exercised on FPGA.

 

Features

  • 32-bit RISC-V ISA CPU core.
  • Support RISC-V integer (I), multiplication and division (M), and CSR instructions (Z) extensions (RV32IMZicsr).
  • Supports user, supervisor and machine mode privilege levels.
  • Basic MMU support – capable of booting Linux with atomics (RV-A) SW emulation.
  • Implements base ISA spec v2.1 and privileged ISA spec v1.11.
  • Verified using Google’s RISCV-DV random instruction sequences using cosimulation against C++ ISA model.
  • Support for instruction / data cache, AXI bus interfaces or tightly coupled memories.
  • Configurable number of pipeline stages and result forwarding options.
  • Synthesizable Verilog 2001, Verilator and FPGA friendly.
  • Coremark: 2.94 CoreMark/MHz
  • Dhrystone: 1.25 DMIPS/MHz (‘legal compile options’ / 337 instructions per iteration)

 

You can download UltraEmbedded’s RISC-V core here

 

A higher performance core by the same author is available here