Lion RISC-V on VELDT FPGA Board
Lion is a formally verified, 5-stage pipeline RISC-V core. Lion targets the VELDT [...]
RSD RISC-V Out-of-Order Superscalar Core
Developed by Ryota Shioya, RSD is a 32-bit RISC-V out-of-order [...]
biRISC-V – 32-bit dual issue RISC-V
biRISC-V is a 32-bit Superscalar RISC-V CPU with the following [...]
UltraEmbedded RISC-V Core
UltraEmbedded presents a 32-bit RISC-V core written in Verilog and [...]
XiangShan
XiangShan is an open-source high-performance RISC-V core developed by the [...]
VeriGPU is a RISC-V based Open Source GPU
The goal of VeriGPU is to Build an opensource GPU, [...]