The Klessydra processing core family is a set of processors that are fully compliant with the RISC-V instruction set architecture (ISA) and are pin-to-pin compatible with the PULPino Riscy cores. The Klessydra-fT13 is a 32-bit processor that uses temporal and spatial redundancy to provide fault tolerance. It supports the RV32IM subset of the RISC-V ISA and is based on the Klessydra-T13 microarchitecture.

 

The Klessydra-fT13’s redundant architecture consists of three hardware threads that each have their own set of signals, providing spatial redundancy. These threads also follow the same instruction in an interleaved fashion, providing temporal redundancy. The writeback results from each thread are buffered and then voted on and written back to the register file only after the last thread has executed, to avoid writing back potentially faulty results. This allows the processor to use a single voted TMR register file in the writeback stage. Additionally, there is interlocking and bypass logic in the pipeline to allow operands to be directly passed among threads, reducing the risk of long stalls.

 

You can download the Klessydra Fault Tolerant processor here