SiFive Performance processors deliver unparalleled performance in an energy-efficient small footprint
The SiFive Performance family of RISC-V processors is designed for maximum throughput, while preserving power efficiency for workloads as varied as branch-intensive operating systems, and multimedia processing. Ranging from 8-stage, dual-issue, in-order architectures equipped with 256-bit vector engines, to advanced three and four-issue out-of-order processors, with and without vector compute capabilities, with best-in-class industry benchmark performance, the SiFive Performance Family represents the future of V compute.

 

There are several cores available from the Performance series.

 

SiFive Performance P600

The latest generation SiFive Performance P600-Series processors are the highest performance commercially licensable RISC-V processors.

The P670 vector application processor features a thirteen-stage, four-issue, out-of-order pipeline and offers best-in-class performance, with >50% uplift over the SiFive Performance P550, while maintaining a significant performance-per-area advantage compared to the Arm® Cortex®-A78.

For applications that don’t require vector compute, or for more area-constrained markets, the P650 offers similar performance levels in a smaller area footprint.

 

  • Full support for the RVA22 RISC-V profile specification for enabling 64-bit apps processors running feature rich OS stacks such as Linux and Android.
  • Breakthrough RISC-V performance
    • Coherent, multi-core, multi-cluster processor configurations, with up to 16 cores
    • Highest performance commercially licensable RISC-V processor achieving >12
  • >12 SpecINT2k6/GHz (P670 Processor)
    • 2x 128-bit RISC-V Vector ALUs compliant with the ratified v1.0RISC-V Vector specification
    • RISC-V Vector Cryptography extension (P670 Processor)
  • P600-Series Architectural Features
    • 64-bit RISC-V core with extensive Virtual Memory Support
    • Four-issue, out-of-order pipeline tuned for scalable performance
    • Private L2 Caches and Streaming Prefetcher for improved memory performance
    • SECDED ECC with Error Reporting
  • Enabling next generation high performance applications
    • RISC-V Hypervisor Extension and System-Level Virtualization IP
    • Advanced interrupt controller with support for MSI style interrupts and virtualization
    • SiFiveWorldGuard System Security
    • Cache stashing to L3 for tightly coupled accelerators

 

You can check out P600 processor ip from SiFive here

 

SiFive Performance P500

The  SiFive Performance P500 application processor features a thirteen-stage, triple-issue, out-of-order pipeline compatible with the RISC-V RV64GBC ISA. The Performance P500 scales up to four-core complex configurations while delivering 30% higher performance in less than half the area of a comparable Arm Cortex-A75.

 

  • Breakthrough RISC-V performance
    • Multi-core, multi-cluster processor configuration, up to 8 cores
    • 3x Performance per mm2 compared to Arm® Cortex®-A75
    • Performance >8.6 SpecINT2k6/GHz, higher single thread performance than Arm Cortex-A75
  • P500 Core Architectural Features
    • 64-bit RISC-V core with Sv39/Sv48 Virtual Memory Support
    • Three Issue, out-of-order pipeline tuned for scalable performance
    • Private L2 Caches and Streaming Prefetcher for improved memory performance
    • SECDED ECC with Error Reporting
  • Enabling next generation applications
    • Cache stashing to L3 for tightly coupled accelerators

     

You can check out P500 processor ip from SiFive here

 

SiFive Performance P400

The SiFive Performance P400-Series application processors are SiFive’s first efficiency-focused Out-of-Order processors. The P400-series is derived from the successful and mature P500-Series, with considerable finely-tuned optimizations for best-in-class performance efficiency and compute density.

 

The P470 vector application processor, with a 128-bit RISC-V Vector ALU, is capable of 2x the single thread performance of an Arm Cortex-A55, achieving >8 SpecINT2k6/GHz, still within similar area and power budgets, representing a significant upgrade to legacy efficiency class cores currently available.

 

For applications that don’t require vector compute, or for more area-constrained markets, the P450 offers similar performance levels in a smaller area footprint.

 

  • Full support for the RVA22 RISC-V profile specification for enabling 64-bit apps processors running feature rich OS stacks such as Linux, Wear OS, and Android.
  • Best-in-class RISC-V performance efficiency
    • Coherent multi-core, multi-cluster processor configuration, up to 16 cores
    • Performance >8 SpecINT2k6/GHz, twice the single thread performance of the Arm® Cortex-A55® (P470 Processor)
    • 1x 128-bit RISC-V Vector ALU, compliant the ratified RISC-V Vector specification as well as the (P470 Processor)
    • RISC-V Vector Cryptography extension (P470 Processor)
  • P400-Series Architectural Features
    • 64-bit RISC-V core with extensive virtual memory support
    • Three issue, out-of-order pipeline tuned for scalable, highly efficient performance
    • Private L2 Caches and Streaming Prefetcher for improved memory performance
    • SECDED ECC with Error Reporting
  • Enabling next generation Wearable and Consumer applications
    • Advanced interrupt controller with support for MSI style interrupts and virtualization
    • System Level Virtualization IP
    • Cache stashing to L3 for tightly coupled accelerators

 

You can check out P400 processor ip from SiFive here

 

SiFive Performance P200

The SiFive Performance P200 is an 8-stage, dual-issue, highly efficient in-order pipeline compatible with the RISC-V RV64GBCV ISA. With full support for the RISC V Vector Extension v 1.0RC, and combined with the SiFive Recode utility, which translates existing SIMD software from popular legacy architectures to RISC-V Vector assembly code, the P200 is an ideal replacement for dated SIMD architectures.

 

  • 256-bit vector length processor
    • Variable length operations, up to 256-bits of data per cycle, with dynamic vector length configuration
    • Ideal balance of control and data parallel compute
  • Performance benchmarks
    • 5.75 CoreMarks/MHz
    • 3.25 DMIPS/MHz
    • 4.6 SpecINT2k6/GHz
  • Scalar processing built from U7 series core
    • Multi-layer Caching support for optimum data movement
    • Stride Prefetcher
    • Virtual memory support, up to 48-bit addressing
  • High performance, flexible connectivity to SoC peripherals
  • Implements RISC-V Vectors v1.0
  • Dual issue scalar unit runs concurrently with vector unit
  • Key vector unit attributes
    • VLEN = 256. DLEN = 128 (datapath width). ELEN = 64 (datatypes)
    • Separate memory and ALU pipelines for concurrent operation
    • Vector operations, decoded and queued in Vector Unit for parallel operation of Scalar and Vector units
  • Vector ALU
    • 128b ALU can perform 2x64b, 4x32b, 8x16b, 16x8b ops/cycle
    • Integer and Floating point data types supported
  • Vector Loads/Stores are 128b/cycle
    • L2 cache treated as primary memory
    • Load from L1 cache, initiates L2 cache load in parallel, minimizing L1 cache miss impact
  • Multi-core, multi-cluster processor configuration, up to 8 cores

You can check out P200 processor ip from SiFive here