The Fraunhofer IPMS offers a processor IP Core based on the RISC-V architecture. This open instruction set architecture (ISA) enables the development of highly application-optimized RISC processors. The IP Core EMSA5 is available as a general purpose variant and as a safety variant with ASIL-D ready certification according to ISO 26262:2018 for functional safety and is therefore suitable for use in safety-critical systems in vehicles. The EMSA5 is supported by several IDEs and thus enables efficient and professional software development for complete systems, also in the context of functional safety according to IEC 61508 and ISO 26262.

 

The RISC-V IP Core can be made available for different FPGA platforms independent of the platform. Integration into customer-specific ASIC developments for any foundry technology is also possible. The Fraunhofer IPMS also provides services to expand the processor core IP with customer-specific modules and to provide complete subsystems.

 

The Fraunhofer IPMS has many years of experience in IP core design and more than 150 IP core users worldwide – a large part of them are used in the automotive industry, aerospace and in the manufacturing industry.

 

Key features:
  • 32-bit, 5-stage pipeline architecture
  • RISC-V Extensions: E, C and M (configurable)
  • Privileged Instructions: Machine (M) and User/Application (U) mode
  • Physical memory protection (PMP)
  • Hardware trigger module and performance counter
  • RISC-V compatible debugger
  • AHB lite interface
  • Extensive coordinated peripheral components

 

Available RISC-V IP Cores:
  • RISC-V IP Core EMSA5-GP – General Purpose
  • RISC-V IP Core EMSA5-FS – Functional Safety

 

You can check out the EMSA5 RISC-V series here