RISC-V’s compressed instruction (RVC) extension is intended as an add-on to the regular, 32-bit instruction set. Its designers designed RVC instructions to be expanded into regular 32-bit RV32I equivalents via a pre-decoder. This core is targeted at “smaller-is-better” applications with few actual instruction-throughput requirements. The Verilog implementation is incredibly small (< 500 lines of code).

 

“Minimax” is an experimental RISC-V implementation intended to establish if an RVC-optimized CPU is, in practice, any simpler than an ordinary RV32I core with pre-decoder.

 

Features:

  • 1 clock per instruction (CPI) using a 2-port register file. RVC instructions have only 1 rd and 1 rs field. A 2-port register file maps cleanly into a single RAM64X1D per bit.

  • A simplified 16-bit instruction path without alignment considerations. The processor is a modified Harvard architecture, with a separate 16-bit instruction bus intended to connect to a second port of the instruction memory. On Xilinx, the asymmetric ports (16-bit instruction, 32-bit data) are reconciled using an asymmetric block RAM primitive. As a result, we don’t have to worry about a 32-bit instruction split across two 32-bit words.

 

You can download the Minimax core here